Company representative reported about the creation of a unique chip SRAM on the SOI substrate with the norms of 14 nm transistors and FinFET. The minimum operating voltage of the storage unit was 0.3 V. Previously, Intel demonstrated the processor Claremont has an operating voltage of 0.4-0.5 V. IBM, as we see, has gone further. At the same time IBM has implemented such a scheme improve dynamic power, which is a slight increase in voltage on the SRAM bit line promises to greatly speed up the memory array.
The source did not disclose the details about the proposal by IBM technology. We can assume that we are talking about semiconductors operating at voltages close to the threshold . At the same time, technologies are proposed which allow to reduce the operating voltage to the gates of transistors without reducing the level threshold. This so-called offset power node when the transistor is supplied 0 voltage (positive or negative). Then the power to the control electrode can be reduced by the amount of displacement, generally saving on consumption. Similar technology in its time also was proposed by IBM. IBM idea to its logical conclusion brought STMicro company , a week earlier on the base of the development , GlobalFoundries company announced the creation process technology 22FDX (22 nm on the substrates FD-SOI). Perhaps in the new technology, IBM combines both methods.
What is important, IBM promises scaling technology works with a dynamic voltage to increase production rates of 7 nm or even lower. It is encouraging that IBM has decided to move away from the traditional scheme of creating a Power-hungry solutions with maximum performance and join the army of developers of energy efficient CPU architectures.