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ARM support for 7-nm process technology TSMC package for designers


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ARM support for 7-nm process technology TSMC package for designers


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POSTER: computer news   ||   ARM SUPPORT FOR 7-NM PROCESS TECHNOLOGY TSMC PACKAGE FOR DESIGNERS

DATE:2016-12-09

In official press release, ARM company announced the availability of Artisan physical IP package for the design of chips, taking into account features of 7-nm FinFET process technology  TSMC.  In particular, package licensing rights acquired by Xilinx to design FPGA-matrices,  SoC and other products.  It is expected that the first digital designs using ARM Artisan platform will appear in the first half of 2017, and the chips samples in the 7-nm silicon will be released before the end of the same year.

Ready platform for designing a 7-nm chips allows rough estimate the benefit from the transition to the current 16-nm solutions in the 7-nm.  Now ARM representatives suggested that the 7-nm chips will help keep productivity at 3 GHz, while reducing consumption by 20% compared to 16-nm FinFET process technology.  We also add that Artisan IP package for the 7-nm TSMC does not allow for the use of EUV-lithography, and relies solely on advanced immersion lithography with a 193-nm scanners.

ARM Artisan IP Package for the 7-nm process technology required significant improvement.  Firstly, in the transition to the 7-nm process designers face the background (natural) radiation will affect the operation of any part in the memory chip.  Second, the wiring conductors becomes more challenging due to the effects of such efforts as crosstalk and electromigration.  Third, to reduce the chip area of an additional agreement with the metallization layer (BEOL) and crystal (FEOL).  Each of these tasks, the new package helps to solve successfully.

All memory is now supported by the hardware error correction mechanisms to reduce the effect of radiation.  Electromigration and noise can reduce the special package that is responsible for power distribution lines.  Optimization of power wiring allows to reduce by 10% the use of the chip area increases and the crystal surface recycle by 20% (from 60% to 80%).  Designing metallization layer now takes into account more nuanced chip architecture.  Additionally, the package is implemented memory array design method taking into account the SRAM memory cell structure that allows  to optimize the arrays.  


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