For the Dutch company ASML, engaged in the development and manufacture of equipment for semiconductor lithography, the beginning of the year was very good. The number of orders for scanners of the EUV (13.5 nm) range has grown and active purchases of 193-nm scanners, optimal for the production of memory and logic with the norms of 10 and 7 nm, are continuing. Executed applications for the purchase of EUV-scanners include 21 installations. The total cost of the order is 2.3 billion euros ($ 2.46 billion). It's about the latest NXE scanners: 3400B. In addition, the company intends to upgrade the 14 previously sold NXE systems: 3300 and NXE: 3350. New and modernized plants will be able to process 125 plates per hour, with an efficiency of 90%, which allows us to talk about the soon-to-be commercial application of EUV lithography.
The names of customers for EUV-scanners were not disclosed. In total, ASML has five customers, which obviously include Intel, TSMC, Samsung and GlobalFoundries. Negotiations are being held with two more companies, whose names are also not disclosed. ASML assures that the chip makers have become more interested in EUV equipment. Of the well-known, it can be recalled that in part the EUV scanners TSMC will begin to use for the release of 7-nm chips of the second generation and completely wants to switch to EUV-scanners for the release of 5-nm solutions. Samsung adheres to a similar plan, although it can start using EUV-scanners already in the first generation of 7-nm process technology. As for Intel, it will start using the latest equipment for the release of 5-nm solutions.
In the first quarter of 2017, ASML generated 1.94 billion euros (about $ 2.08 billion). Revenue has consistently increased by 2% and 46% per year. Net profit for the period was $ 452 million euro ($ 484 million). Consistently quarterly profit decreased by 14%, but in annual terms increased by 128%. In the second quarter, the company expects to raise from 1.9 to 2 billion euros.
In conclusion, we add that ASML has entered into a partnership agreement with Cadence Design Systems. Cadence's design tools will include models and ASML scanner profiles. This will allow developers to test the design of chips before making solutions - even at the design stage. Such an innovation will reduce the probability of errors in the stage of the first silicon output and shorten the production cycle.