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 - Huawei V9 announcement date - MediaTek announces 8-core 16-nm mobile chips Helio P23 and Helio P30 - Western Digital acquires a developer of flash arrays - Specifications PCIe 4.0 will see the light this year, and PCIe 5.0 in 2019 -


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POSTER: computer news   ||   HUAWEI V9 ANNOUNCEMENT DATE

DATE:2017-08-30

There is new information about a mysterious smartphone Huawei, which, according to sources, was to be called Honor V9 Mini.  In fact, the novelty will be called Huawei V9 Play and will be presented next week.  

Huawei announced on its page in the social network Sina Weibo that its next smartphone will be presented on September 6, on Wednesday.  This will be Huawei V9 Play, a smartphone of the middle class with the appropriate characteristics and price tag.  It will include a HiSilicon Kirin 659 processor, 4 GB of RAM, a fingerprint scanner and a 12-megapixel main camera.  Huawei V9 Play will go on sale at a price of 1500 yuan .

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Huawei V9 announcement date

Huawei V9 announcement date

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HUAWEI V9 ANNOUNCEMENT DATE

POSTER: computer news   ||    MEDIATEK ANNOUNCES 8-CORE 16-NM MOBILE CHIPS HELIO P23 AND HELIO P30

DATE:2017-08-30

MediaTek announced two new chips for mobile devices.  They have replenished the series of processors MediaTek Helio.

The new mobile processors MediaTek were told by our colleagues from GSMArena .  This MediaTek Helio P23 and Helio P30.  The first devices based on new chips will appear on the market in the fourth quarter of 2017, although Helio P30 will be available only in China.

 

Characteristics Helio P23:

 

* Processor: 4 cores Cortex-A53 with a clock speed of 2.3 GHz + 4 cores Cortex-A53 with a clock speed of 1.65 GHz;

* Graphics: Mali G71MP2, 770 MHz;

* Modem: LTE Cat 7/13 300 / 150Mbps, VoLTE;

* Support for cameras: dual 13-megapixel camera with single lens and up to 24 megapixels resolution;

* Process: 16-nanometer TSMC.

Characteristics Helio P30:

 

* Processor: 4 cores Cortex-A53 with a clock speed of 2.3 GHz + 4 cores Cortex-A53 with a clock speed of 1.65 GHz;

* Graphics: Mali G71MP2, 950 MHz;

* Modem: LTE Cat 7/13 300 / 150Mbps, VoLTE;

* Support for cameras: dual 16-megapixel camera with single lens and resolution up to 25 megapixels;

* Process: 16-nanometer TSMC.

Also worth noting that both chips have support for DSDS (Dual Sim Dual Standby) mode, which allows to install LTE connection from both SIM cards.

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MediaTek announces 8-core 16-nm mobile chips Helio P23 and Helio P30

 MediaTek announces 8-core 16-nm mobile chips Helio P23 and Helio P30

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MEDIATEK ANNOUNCES 8-CORE 16-NM MOBILE CHIPS HELIO P23 AND HELIO P30

POSTER: computer news   ||    WESTERN DIGITAL ACQUIRES A DEVELOPER OF FLASH ARRAYS

DATE:2017-08-30

According to a recent press release from Western Digital, the manufacturer agreed to purchase a startup in the flash memory market - Tegile Systems.  The amount of the transaction is not disclosed.  The parties intend to close the deal before September 4.  Together with experts from Tegile Systems, Western Digital will receive unique developments for server storage systems and about 1,700 customers for the respective products.  For example, just a week ago we talked about a new series of rack storage systems Tegile IntelliFlash N on flash memory (SSD) with end-to-end support for the NVMe protocol.  Demand for similar systems with advanced functionality and full orientation to solid state drives is steadily growing, which opens up a lot of new prospects for Western Digital.

It should be noted that Western Digital and SanDisk started investing in Tegile Systems in 2013, shortly after in 2010 Tegile appeared on the horizon of the market of hybrid storage systems.  Even then, four years ago, Western Digital and SanDisk were named strategic partners of Tegile.  Now, as we know, the first Tegile systems used custom-built SanDisk SSDs (the new Tegile systems use the conventional SSD standard form factor).  As for Western Digital, it then directly stated that it will work with Tegile to develop and promote hybrid storage systems on HDD and SSD.  Today, as we understand (after the acquisition of SanDisk), Western Digital is more interested in promoting flash arrays.

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Western Digital acquires a developer of flash arrays

 Western Digital acquires a developer of flash arrays

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WESTERN DIGITAL ACQUIRES A DEVELOPER OF FLASH ARRAYS

POSTER: computer news   ||    SPECIFICATIONS PCIE 4.0 WILL SEE THE LIGHT THIS YEAR, AND PCIE 5.0 IN 2019

DATE:2017-08-30

We already reported that in July and August the final discussions of the draft specifications of the standard (interface) PCI Express versions 4.0 and 5.0 are conducted.  The PCIe 4.0 version received the ordinal number 0.9, which is close to the final approval of the standard, and the PCIe 5.0 version is ready in stage 0.3, which means a fairly early stage of the process.  Nevertheless, the process is on its way, and at the recent annual Hot Chips 2017 event, representatives of the responsible organization PCI-SIG confirmed the terms of acceptance of the final versions of PCI Express 4.0 and 5.0.

It should be noted that adoption of PCI Express 4.0 specifications has been extremely protracted.  The version of PCI Express 3.0 was introduced in 2010.  The PCI Express 4.0 version will be developed and available to a wide range of developers in late 2017.  Instead of the usual 4-year cycle of updating the standard, the new version had to wait for 7 years.

In the last couple of years the industry has faced a lack of bandwidth of the PCI Express 3.0 bus.  Intensive calculations for the needs of artificial intelligence have chosen the potential of this high-speed interface.  A similar story occurs in the field of corporate data storage, which began with the expansion of SSD with support for the NVMe protocol.  Both these factors, as well as a number of other reasons, lead to the fact that the PCI Express 4.0 standard will be a temporary.  It will be replaced quickly - in 2019 (in two years!) Should come standard PCI Express 5.0 with twice the bandwidth.

For PCI Express 4.0 specifications, as is known, the data transfer rate on one line will be increased from the current 8 Gbit / s to 16 Gbps (conditionally, some of the data in the package goes to the interface maintenance and does not bear useful information).  The PCI Express 5.0 specification provides for a transfer rate of 32 Gbps per line.  As in the case of PCI Express 3.0, the encoding will be 128b / 130b with redundant coding of 1.5%.  Simplified (or aggressive) coding already during the transition from version 3.0 to version 4.0 gives an overall reduction in redundancy of 20%, which will have a positive impact on energy efficiency and on useful throughput.

 

In the fourth quarter, as already mentioned, the adoption of PCI Express 4.0 specifications (final version) and draft specifications PCI Express 5.0 version 0.5 is expected.  A number of vendors have already developed or are completing the development of controllers supporting PCI Express 4.0.  Such a controller, for example, can be found in IBM Power9 processors.  Intel and AMD, according to rumors, before 2020, the PCI Express 4.0 bus in their platforms is unlikely to use.  Or they will surprise us?

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Specifications PCIe 4.0 will see the light this year, and PCIe 5.0 in 2019

 Specifications PCIe 4.0 will see the light this year, and PCIe 5.0 in 2019

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SPECIFICATIONS PCIE 4.0 WILL SEE THE LIGHT THIS YEAR, AND PCIE 5.0 IN 2019

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