Synopsys Introduces Toolkit for Integration into SoC Controllers HBM2

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POSTER: computer news   ||    SYNOPSYS INTRODUCES TOOLKIT FOR INTEGRATION INTO SOC CONTROLLERS HBM2	DATE:2017-07-28
The memory of HBM2 has good prospects in the composition of high-performance platforms.  In comparison with DDR4 memory, the speed of working with HBM2 memory is more by an order of magnitude.  Modern DDR4 specifications allow for exchange at speeds of 3200 Mbit / s, and HBM2 chips can provide up to 307 GB / s throughput, which is 12 times more.  It is this bandwidth that will allow HBM2 controllers, which can be designed using the new Synopsys tool package.   The developer of the tools for digital design reported that he began to distribute the complete set of design tools (DesignWare) of HBM2 controllers.  The kit includes controller design, physical layer design, and tools for testing and self-testing of designed solutions.  The presented kit allows with less effort and as soon as possible to integrate the HBM2 controllers into the composition of any single-chip assembly or processor.  This will speed up the appearance of interesting graphics processors and high-performance server-based processors. Synopsys tools allow you to create a HBM2 controller with a bandwidth that is 20% more than the JEDEC standard (that would be where memory manufacturers provided the HBM2 bandwidth!).  The standard prescribes a maximum data transfer rate of 2000 Mbit / s per contact.  Synopsys design tools guarantee the operation of controllers at speeds up to 2400 Mbit / s per contact.  In addition, the HBM2 controllers, designed with the help of the corresponding Synopsys package, support all the innovations provided by the HBM2 standard, including four consumption modes (for power savings) and pseudo-channel data bus addressing. The breakdown of data access channels into pseudo channels is quite an important innovation, which became available with the advent of HBM2 specifications.  This allowed to increase the speed of memory access with two crystals in the stack.  According to the original standard, only two 128-bit channels can be connected to each crystal in the stack.  In the case of a four-chip stack, the entire available HBM (2) bus is 1024 bits wide, but for a stack of two crystals, half of the channels remain in the "air" and does not work for the throughput of the chip.  In the pseudo-channels (software emulation) mode, each 128-bit channel is divided into two 64-bit channels, which doubles the number of working channels for data access and increases the access speed of small-capacity HBM2 memory (with the minimum number of chips in the stack). Synopsys tools for the design of the HBM2 controller have already been used by AMD designers who, with their help, integrated the controller into the graphics processor on the Vega architecture.  The result reportedly met expectations.  The key to the success of the new Synopsys tools is the widely-used experience from the previous development of the design tools and memory controllers HBM of the first generation and DDR4 memory. Related Products :

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Synopsys Introduces Toolkit for Integration into SoC Controllers HBM2 (2017-07-28)
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