In the new architecture of processors, Intel abandoned the internal ring bus

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POSTER: computer news   ||    IN THE NEW ARCHITECTURE OF PROCESSORS, INTEL ABANDONED THE INTERNAL RING BUS	DATE:2017-06-16
In March, Intel showed an image of a 28-core crystal processor Skylake-SP.  Then we noticed that the location of the cores and interfaces has undergone significant changes.  Yesterday at Intel at one of the home events explained what these design changes are related to.  As it turned out, in the future Intel will refuse (and has already refused for Skylake processors in versions of Xeon and desktop solutions of higher performance) from the internal processor ring bus. The ring bus was introduced in 2008 together with the Nehalem architecture and the Westmere-EX processors.  It was necessary in connection with the increase in the number of core on the crystal.  The developers of Intel used three variants of the design of the processors (depending on the maximum number of cores on the chip) with three variants of the ring bus.  In the most difficult case, the processor inside was divided into two clusters, each of which was serviced by two ring buses.  Between each other, the buses were connected by bi-directional switches with buffering (in the diagram above they are indicated in gray). As the number of core increases, the ring bus has become an obstacle to increasing the capacity and reducing delays.  More precisely, it has become too much to consume, so that it can be scaled in the direction of increasing the speed of data exchange.  Therefore, in the Skylake-SP processors, Intel developers decided to use a different structure for connecting the cores to each other - a well-tested cellular network in the Intel Xeon Phi (Knights Landing) architecture.   Each core in the new architecture has its own switch with a buffer and is connected to any other core within the processor only through two nodes - outgoing and incoming.  This allows the mesh bus to operate at relatively low frequencies and significantly reduce the total interface consumption without degrading bandwidth and increasing latency.  In addition, this communication structure scales very well, allowing Intel to increase the number of cores on the chip in the future without a noticeable increase in the energy costs for internal data transport. Clarifying the essence of the new internal bus, as well as the appearance of the image of the 18-core processor with a new design, also makes it possible to ensure that the new processors do carry an integrated 6-channel memory controller, which is now spread around the edges on the crystal just above the middle.   Related Products :

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