Intel announced that the processor architecture Haswell will be implemented transactional memory mechanism, involving the simultaneous execution of complex multi-threaded operations, but in isolation from each other, which eliminates the collapse of program due to an error in one thread .
The architecture of this mechanism is called Haswell Transactional Synchronization Extensions (TSX), which, in turn, is divided into two main parts: Hardware Lock Elision (HLE), broadcasting the normal programs while preserving transactional efficiency, and Restricted Transactional Memory (RTM)
In today's computer systems, the allocation of resources involved in processing cores operating system, but the developers intend to pass these responsibilities on the hardware. The processor itself will determine when, how and with what data flow it need to work, as the hardware part will deal with memory allocation, deciding what data can share a common memory, which is required for the allocated space.
Such mechanisms are implemented in some products, but Intel intends to introduce support for transactional memory in hardware across the board. However, the developers report about the related technical difficulties, and Haswell processors, are likely to be only an experiment in the development of new technologies.
Intel. Haswell will be coupled with a graphics core in three (GT1, GT2 and GT3), with the GT3's high end product characterized by a 40 execution units. At equal core frequencies Haswell will be 2.5 times faster than Ivy Bridge, or 5 times more productive than the integrated video processors Sandy Bridge.
Haswell processors will work with LGA 1150 and in motherboards based on chipsets Lynx Point.