Synopsys and TSMC have agreed on the elements of 20-nm semiconductor design

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POSTER: computer news   ||   SYNOPSYS AND TSMC HAVE AGREED ON THE ELEMENTS OF 20-NM SEMICONDUCTOR DESIGN	DATE:2012-10-16
Synopsys company announced the completion of its adjustment tools package for developing, testing and production of semiconductors in relation to the 20-nm process technology at the facilities of TSMC.  This is important because TSMC company will start experimental production of semiconductors with a rate of 20 nm within the next year.   Despite the fact that TSMC uses the system design with Synopsys in 2001, adapting the package RTL-to-GDSII Galaxy Implementation Platform has its own perspective.  The fact that this set of EDA-tools (Electronic Design Automation - automation of electronic devices) was developed with an eye (or at least - the original) to service production companies in the Technology Alliance IBM, which includes Samsungand GlobalFoundries company.   Separately, we note that the package for the 20-nm process technology was based on the creation of crystals with a double projection.  This is a necessary measure to use for the production of semiconductors,  old 193-nm scanners.  Theoretically, since the 20 nm is needed to introduce EUV-scanners.  But Intel company , for example , is hoping to hang on 193-nm projection to release 10-nm semiconductor, using five masks for projection on a single die.   Related Products :

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Xtreview Support N-Post:xxxx Xtreview Support	SYNOPSYS AND TSMC HAVE AGREED ON THE ELEMENTS OF 20-NM SEMICONDUCTOR DESIGN
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