Intel Cannon Lake Processors receive support AVX instructions 512
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POSTER: computer news || INTEL CANNON LAKE PROCESSORS RECEIVE SUPPORT AVX INSTRUCTIONS 512 |
DATE:2016-02-23 |
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Intel has already implemented support for its processors with two generations of vector instructions AVX (128-bit AVX 256-bit AVX 2). Supports for 512-bit AVX 3 instructions in skylake was expected , but in fact it turned out that the regular version skylake do not support 3. Support for AVX 512-bit instructions in Intel products begin with Xeon processors generation Skylake-EP Xeon and the Phi-generation accelerators Knights Landing. Accelerators Knights Landing will not use the whole package of instructions, but they will be the same with future Xeon processors, general purpose. The desktop versions Intel processors support 512-bit instructions with the expected yield of the 10-nm solutions, known to us under the code name Cannon Lake. These processors will be released in the second half of 2017. And indeed, Cannon Lake processors will support 512-bit instructions. The server version of Xeon get support sets AVX512F, AVX512CD, AVX512DQ, AVX512BW and AVX512VL. Since Skylake-EP and Cannon Lake will be released in the second half of 2017, it was during this period will have a massive adaptation of programs for compatibility with 512 AVX instructions sets. AMD , we recall, in the processors with the architecture Zen will naturally support only 256-bit AVX instructions, although the execution of 512-bit instructions will be also possible due to the simultaneous use of 256-bit blocks. | ||
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INTEL CANNON LAKE PROCESSORS RECEIVE SUPPORT AVX INSTRUCTIONS 512 |
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