TSVs is relatively new technology - , which involves the creation of vertical wires (metalized channels) between upper and lower crystals in the stack. Feedthrough narrow footprint chip to chip area and save consumption by drastically reducing the lengths of connections. In addition, for short wire significantly increases the rate of exchange.
Yesterday about the latest success in the field of practical implementation of TSVs-compounds reported GlobalFoundries company. According to an official press release from the manufacturer, the American company's factory - Fab 8 - managed to get the first plate with work items of 20 nm using a vertical cross-connections. This complex process is implemented for the so-called process technology 20nm-LPM. It is not suitable for the production of the CPU, but it is suitable for mobile applications, to produce solutions for the consumer electronics and production controllers. Hopefully, the manufacturer adopts TSVs for something better.
For the release of 3-D semiconductors with through connections GlobalFoundries uses so-called via-middle process. The approach is to fill the holes for copper plating on the penultimate stage of the proceedings, when the whole set is made of crystals, and the package has not yet been carried out. This avoids problems with the two-layer metal (copper) connections at the time of manufacture of each layer, where the operating temperatures for copper are extremely high.
The first commercial solutions using TSVs-compounds the company will not release until 2015.
JEDEC is close to the assertion of the memory interface, as Wide IO (up to 12 Gbit / s). One package contains a memory interface Wide IO can be used up to four crystals with conventional wire . Release this memory is easier than in a stacking configuration, so Texas Instruments and STMicroelectronics company, for instance, abandoned the idea of working with TSVs.
Finally, the packing stack memory and other crystals can only deal with companies that specialize in this activity type - Amkor, ASE and others. It is clear that it will not make the final chip cheaper. All because of the complexity of multi-dimensional packaging of chips when you need to separate each crystal from the time the carrier substrate and then link them together. Related Products :
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