The traditional technology of NAND flash memory will last for two generations of process technology

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POSTER: computer news   ||   THE TRADITIONAL TECHNOLOGY OF NAND FLASH MEMORY WILL LAST FOR TWO GENERATIONS OF PROCESS TECHNOLOGY	DATE:2013-05-26
During the event, Imec Technology, held this week in Belgium,  IM Flash Technologies company, a joint venture between Intel and Micron Technologies, has shed light on the development of plans for the three-dimensional layout of chip technology in the production of flash memory. The industry is now beginning to shift from planar placement of NAND memory cells to layout with vertical integration of transistors.  This approach allows us to form a cell capable of storing multiple bits of information due to the presence of the vertical channel and a gate corresponding to different stress levels  . The leader of the company direction was Toshiba, which has developed technology  p-BiCS (pipe-shaped Bit Cost Scalable).  Late last year, the Japanese manufacturer announced the creation of 16-layer memory that uses a vertical channel with a diameter of 50 nm.     According to IM Flash Technologies, limit reduction of traditional flash memory is already close, but the existing technology will suffice for another two-generation technology standards - 15 and 10 nanometers - .  The development of three-dimensional layout unfold on stage, corresponding to 15 nm.  Interestingly, the 16 layers, as calculated by IM Flash Technologies, is not enough to make the venture economically viable.  At least to 32, and more preferably - 64 layers. Related Products :

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