Ten years ago, processors developers believed that to optimize the performance of specific tasks may be due to the involvement of specialized co-processors in the concept of Torrenza, but recently even AMD calls build custom blocks directly to the CPU.
Intel has similar ideas , this week published a press release in which the processor giant announces the start of cooperation with the Californian company eASIC, creating adaptable for specific tasks chips. It is expected that Intel will build programmable blocks into their processor Xeon. This will attract customers to expedite specific tasks. In contrast to the programmable matrix FPGA, such an arrangement would lead to higher energy efficiency, albeit at the expense of versatility. In addition, solutions eASIC productive FPGA, which is also important for potential clients.
Obviously, the processor giant headed for the possibility of adapting its server processors to the needs of specific customers. Now eASIC release products on 28-nm technology at TSMC. Obviously, access to advanced lithography technology will allow Intel the first companies to expand their own capabilities.