SRAM design with only one transistor

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POSTER: computer news   ||   SRAM DESIGN WITH ONLY ONE TRANSISTOR	DATE:2015-12-13
The fastest memory for embedded applications remains SRAM memory type .  As part of the processor SRAM memory is used in cache and takes a lot of space today .  Reduce the area of SRAM array is not so simple.  For reliable operation, each SRAM cell must consist of 4-8 transistors.  This reduces the sensitivity to noise in the circuits .   Zeno Semiconductor  company,  in the conference International Electron Devices Meeting in 2015 spoke about architecture 1 transistors cell SRAM. Strictly speaking, a bipolar transistor NMOS-Zeno - is two transistors in one.  As it appears, it is shown in the diagram above.  But even such a structure allows to save space.  It is reported that 28-nm SRAM Zeno cell occupies an area of 0,025 square meters.  m.  For comparison, a typical SRAM occupies 0,127 square meters.  m.  Cell SRAM Zeno even less than 37% of 10-nm SRAM Samsung cell using FinFET transistors, which occupies 0,040 square meters.  m.  Another advantage of the development promises to be a reduction in leakage current.  The company also offers two types of architecture. 1 transistors for efficient devices and totem performance.  In both cases, the cell area will be many times smaller than current solutions. Development of the company is protected by over 50 patents.    However, once again we emphasize that there is no evidence of the reliability of a new architecture  SRAM memory, : Related Products :

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