AMD Jaguar supports AVX and SSE4

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POSTER: computer news   ||   AMD JAGUAR SUPPORTS AVX AND SSE4	DATE:2013-02-20
At the present stage of development microprocessor products were in demand with low power consumption, designed for use in mobile devices.   At the conference, ISSC 2013 AMD has released new details about Jaguar microarchitecture  . Hybrid processors based on Jaguar will be designed on 28-nanometer HKMG technology at the facilities of TSMC.  In the configuration of the new APU will enter up to four x86-64 cores.  Core are completely independent (as opposed to core modules in Bulldozer, that share the unit).  Core will work together with 2-MB cache second level. Jaguar used 40-bit physical address (Bobcat - 36-bit), per cycle load / store processor will be able to send 16 bytes of data, which is twice the possibility of Bobcat.  Data bus FPU - 128-bit, which is also twice that of Bobcat.  Scheduler queue depth increased by about 50%.  There is a possibility of an extraordinary command execution, inherited from Bobcat.  As for the instruction set, the developers have added expansion teams ISA, typical of big processors, such as AVX and SIMD (SSSE3, SSE4.1, SSE4.2 and SSE4A), widely used in today's multimedia applications .  In addition, was added AES-NI, accelerating encryption algorithm AES. Energy efficiency, according to AMD, was increased due to full power down inactive cores to help improve the performance of autonomous mobile devices.   Related Products :

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