Intel Look at multistage chips

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POSTER: computer news   ||   INTEL LOOK AT MULTISTAGE CHIPS	DATE:2015-02-23
Intel company is prepared for the event ISSCC 2015.  First of all, Intel is determined to master the production of 10-nanometer chips, and promises to spend half the time than in the case of a 14-nm process technology.  The latter, as it turns out, it took some optimization at the level of photomasks and took more time to reach an acceptable level   than originally planned.  Problem areas during the development of Intel 10-nanometer technology promises to pay close attention, so there should be no delay.   The use of 10-nm technology does not require a transition for immersion lithography.  Of course, the use of available tools will complicate and increase the cost of the technology, but in the end everything has to be paid back.  Daylight immersion lithography takes longer than planned, so Intel is not in a hurry to master this step as part of a 10-nm process technology. If AMD and NVIDIA are already calling the specific product, which will use the so-called 2.5D-layout and memory type HBM (this is Fiji and Pascal, respectively).  It is noteworthy that the processor giant considers the use of 2.5D and 3D layout relevant in the segment of smartphones and tablets, where the requirements for compact size can justify a marked increase in the cost of accommodation tiered heterogeneous logic.  Layers chips can be produced by different technological standards, and it is to a certain extent untie the hands of developers: the most critical function blocks can be made on the finer process technology, and save the rest.  By the way, Intel believes that even in conditions of mass production cost of multilevel chips will remain high, and it can be justified only in specific market segments. Related Products :

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