Zen core becomes monolithic with the support of multi-threaded (SMT) calculations. Each core will have 6 conveyors ALU for operations with integers and two 256-bit module for processing 256-bit floating-point operations (FMAC, fused multiply - add capability).
Valdhauer Matthias- blogger from Germany, for a long time writing on the topic of processor architectures, offered his compilation of Internet leaks and rumors. There was the following scheme, part of the data for which he learned from a new patch for AMD processors with Zen architecture .
According to AMD's patch comments, the program should refer to the 4 ALU, 2 AGU (address generation unit) and 4 FPU. Total per core Zen there are ten pipelines for data processing, while two cores Excavator whole accounts for 10 conveyors. 4 Pay attention to the FPU. In the scheme presented in the spring of blocks for processing floating-point data represented by two 256-bit FMAC. In fact it may be that each of them consists of a pair of 128-bit FPU, one for operations and one for the multiplication addition operations. This somewhat reduces the delay in the performance of commonly used floating-point operations, but such a design, according to the author, also means that Zen core will not conquer high clock speeds (the focus is on increasing the number of operations per cycle, rather than increasing the number of cycles). This is one hope for the 14/16-nm process technology, which can help reduce the consumption of CPU Zen and due to this it will be possible to raise the frequency. Related Products :
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