An effective solution for memory controllers at a rate of up to 20 Gbits per lane

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POSTER: computer news   ||   AN EFFECTIVE SOLUTION FOR MEMORY CONTROLLERS AT A RATE OF UP TO 20 GBITS PER LANE	DATE:2015-10-15
Toronto University developers have designed and produced using the 28-nm transceiver signals to one input that can transmit data on the line at a speed of up to 20 Gbit / s.  Consumption of the solution is 3 pJ per bit.  It is argued that this is the best at the moment ratio.  It managed to reduce consumption, since it use the scheme used passive EQ signal, and the stability of receiving data provided by its own reference oscillator signal receiver.  Also, the advantage of a passive equalizer that there is no interference on power. Unfortunately, the authors of the project did not specify for what type of memory they created their decision.  One line memory interface HMC in the second generation of the standard is capable of transmitting data at speeds up to 30 Gbit / s (15 Gbit / s in the first generation).  One line memory interface HBM-to-date first generation is capable of delivering up to 1 Gbit / s.   Related Products :

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