More details about the structure of shared L3 cache in AMD Zen processors
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POSTER: computer news || MORE DETAILS ABOUT THE STRUCTURE OF SHARED L3 CACHE IN AMD ZEN PROCESSORS |
DATE:2016-08-23 |
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AMD has continued to make public information about Zen architecture data. On ComputerBase.de site you can find a whole heap of slides with the structure of certain Zen-generation processor blocks. The new architecture will be the base of processors in the entire possible range - from tablets and game consoles to desktop and server systems. For example, certain types of energy-efficient cores Jaguar will be removed . AMD Raven Ridge processors with TDP of 4W will be held on the same core structure as well as a 32-core processors Naples. Such an approach will reduce development costs the entire spectrum of products and facilitate the production of new products.  The second point, which is now possible to clarify - this is the ideology of the work and structure of the unit shared cache L3 Zen processors. Block L3 cache is integrated with the access module or CPU Complex (CCX). One module serves simultaneously four cores Zen with each access to any portion of the L3 with approximately the same average latency. When this bandwidth when accessing the L3 Zen memory over the previous architecture may be increased to 5 times. This is achieved by a 2-fold increased bandwidth when accessing the L2 memory and L1 and L3 due to decomposition into four separate large area with an additional memory of each partition in two more. This allow to organize a 16-way set associative L3 and to have a significant impact on the performance of AMD Zen processors.  The company also reported about the integrated memory controller and PCI Express bus, which also has a decisive influence on the performance of the processor architecture. Related Products : | ||
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MORE DETAILS ABOUT THE STRUCTURE OF SHARED L3 CACHE IN AMD ZEN PROCESSORS |
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