Samsung company until the end of the year plans to expand the mass production of 10-nm chips using FinFET transistors. An important part of each processor is a memory array of SRAM type . SRAM Area as part of the processor takes up about 30%. This SRAM cell design is complex and consists of 4-8 transistors (often - out of six). . At the conference, International Solid-State Circuits Conference (ISSCC ) 2016, Samsung said that compared with the second generation 14-nm process technology to 10-nm SRAM cell will decrease the area by 38%.
Reduction of 6-T cells by 38% - a good compression, which will give the effect. It should be clarified that the compression effect is true for circuits with focus on the transistor density. If we talk about the size of a cell for high-performance processors (for which the density can be sacrificed), the area of the cell was left at the level of the previous 14-nm process technology, although the cell has changed. Because of problems with the reduction process technology standards in the chain of SRAM cells for release within the 10-nm lithography had to add additional elements. Also, Samsung noted the lack of progress in reducing the internal resistance of the cell, which will limit the SRAM performance .
However, it is prematurely to speak about the performance characteristics of 128-Mbit chip SRAM . While this is only a digital project that has yet to reach the silicon, Separately, Samsung points out that the 10-nm process technology is 10 nm in all - in the wiring layers in the metallization in the vias, in the thickness of the wire and so on. Related Products :
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