TSMC urges change to the design of chips

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POSTER: computer news   ||    TSMC URGES CHANGE TO THE DESIGN OF CHIPS	DATE:2017-02-07
On Monday kicked off an annual conference Solid State Circuits Conference (ISSCC), where industry leaders talk about their achievements.  We hope for a lot of interesting information, but for now start with the message about the performance of  TSMC chief research arm , Cliff Hou .  The head of the world's largest chip maker developers said that over the years the current semiconductor design paradigm is outdated and needs to be replaced. According to him, over the past ten years, designers have become skilled in developing of SoC mobile, surround  with the proper tools and gaining specific experience.  Meanwhile, the experience and tools, as well as databases with elements for automatic design (EDA) are not well suited for the other three new areas: electronics for automobiles, items with an Internet connection and machine learning.   The transition to a new paradigm and tools are also due to the considerable complexity of design in recent years.  For example, the transition from 40-nm to 7 nm resistance metal layers doubled that every time it was necessary to take into account.  We can add more and more frequent use of vertical connections (columns or holes for metallization), a manufacturer with its own problems.  Besides TSMC use two different metals for metallization and contacts depending on required speed or high density arrangement of elements on the chip.  Ideally, all this must be considered in the design of automatic systems, chips and be able to rebuild on the type of problems . Equally important  was to focus on the power distribution inside the chip.  The density of the elements becomes impossible to apply the necessary power to all memory cells in the chip.  For the experienced 7-nm process technology is considered a good result be powered up to 74% of the cells.  If the power distribution design with special care, it is possible to use up to 79% of the cells.  A further reduction of process technology scale further complicate this task.  This means that the instruments main circuit chip design requires special attention. Finally, automatic chip design tools necessary to implement machine learning.  Already at this early stage in the design of the advantages seen with the "AI".  As an example shown TSMC as before routing system using prediction bottlenecks chip could thus alter the final design, it is allowed to increase to 40 MHz clock frequency of the solutions.  AI also allows the management of large groups of objects than can engineer.  TSMC has already begun to change the attitude to the chip design methods. Related Products :

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