IBM reported a breakthrough in the development of the technical process with a rate of 5 nm

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POSTER: computer news   ||   IBM REPORTED A BREAKTHROUGH IN THE DEVELOPMENT OF THE TECHNICAL PROCESS WITH A RATE OF 5 NM	DATE:2017-06-06
A couple of weeks ago, Samsung admitted that risky production with a 5-nm standard will begin in 2019.  True, the emphasis during the report on the development of new technical processes was made on a 4-nm production rate, but this does not change the essence.  Transistors with 4 and 5 nm standards will get a new structure.  At Samsung, it's called the multi-bridge channel FET or MBCFET.  Externally, this is the same silicon fin FinFET, only now it is not integral.  The silicon channel from the monolithic rib turned into several silicon jumpers (they can be seen in the section on the photo below), surrounded on all sides by the shutter material.  This significantly increased the gate area and the ability to adjust the currents, and significantly reduced leakage. "Responsibility" for the development of MBCFET or, in general, GAAFET (gate-all-around FET), was taken over by IBM.  The development was told yesterday at the VLSI Technology and Circuits conference in Kyoto, Japan.  The development was carried out in cooperation with GlobalFoundries and Samsung, based on the IBM Research Alliance.  From this it follows that the transistors MBCFET with the norms of 5 nm will produce both Samsung and GlobalFoundries.  IBM is confident that this is a revolutionary invention among the many others that the company has made in its history. According to the developers, smartphones on the 5-nm element base will be able to work without recharging for 2-3 days.  More intelligible formulations explain that, in comparison with the 7-nm FinFET process technology, the performance of a 5-nm process with channels in the form of "nanoprawels" will grow by up to 40%.  With the same performance, the power consumption of 5-nm chips will be 75% less than 10-nm chips.  The density of transistors placement will also increase.  So, using an experienced 7 nm process technology, IBM released a chip with 20 billion transistors two years ago.  The process technology of 5 nm will allow to place up to 30 billion transistors on the same area of the crystal. Let's add, for release of 5-nm decisions on the base of transistors from nanostranits and surrounding shutters EUV-lithography will be used.  By this time, lithography with a wavelength of 13.5 nm manufacturers run on the technical process with the norms of 7 nm and, apparently, 6 nm.  In any case, even today all these partners were able to implement in silicon, although it is hardly a question of working chips. Related Products :

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