We have already reported that on motherboards for the new APU AMD Bristol Ridge except the hybrid processor can be located south bridges B350 and A320. At the same time the structure of the new APU allows the company to consider them, if not full-fledged single chip, then, at least, something in between a set of two-chip SoC and logic. To ensure the basic functionality of the APU AMD Bristol Ridge includes all the necessary interfaces for the platform PC, eliminating the need for Southbridge.
As can be seen from the scheme submitted by the author AnandTech site, the APU forces can organize two-channel access to DDR4 memory, supporting two DIMM modules per channel, single port PCI Express 3.0 x8, one port PCI Express 3.0 x4 connection Southbridge B350 or A320 , four ports USB 3.0, two SATA 6 Gb / s, and two lines of PCI Express 3.0 x1 supporting NVMe.
Of the above it is easy to understand that the APU AMD Bristol Ridge are embedded controller PCI Express 3.0 x16, but actually use it to connect the full-length graphics cards with the bus PCI Express 3.0 x16 . Moreover, the proposed new APU port PCI Express 3.0 x8 can not be split up into smaller configurations.
The problem can be solved differently. The diagram below you can see the hypothetical and intended use of PCI Express 3.0 lines, including the installation of PCI Express bridge to separate single port PCI Express 3.0 x8 on two cards. Another thing is the question whether the decision is worth it if one bridge will cost about $ 100?
Other PCI Express lines also can be attached: the line to the south bridge can be used for the organization of two ports Thunderbolt 3 (using Intel set), and two lines for the drive can continue controllers and eight additional ports SATA 6Gb / s.
By the way, despite the fact that the south bridges for Bristol Ridge supports USB 3.1 port 10 Gbit / s, support for symmetric connector USB Type-C in AMD platform is impossible. For the organization on board with Bristol Ridge processor port or two ports with support for USB Type-C will require a number of separate additional chips.
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