Process technology with the norms of less than 5 nm

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POSTER: computer news   ||   PROCESS TECHNOLOGY WITH THE NORMS OF LESS THAN 5 NM	DATE:2016-12-31
The production costs to produce solutions of 5 nm will be 2.5-3 times higher than in the case of manufacture 16/14-nm semiconductor.  SoC design, as reported by Gartner agency, for a 7-nm process will be 9 times more expensive SoC design for the 28-nm process technology will be approximately $ 271 million. Will cost $ 500 million for the 5-nm SoC design. Adding to the problem is that with the technical process 16/14-nm path contract manufacturers with Intel dispersed.  If Intel is offering "fair" process technologies,  TSMC and others use of a contact connection from the previous process technology with the size of the elements (the shutter, edges, and so on) from the process technology with lower standards.  Thus,  Intel process technology from 10 nm standards will have approximately the same characteristics as TSMC process technology with the norms of 7 nm.  This imbalance will also be in the case of 5-nm and 3 nm process.  TSMC process technology with the norms of 3 nm will be accompanied by the same characteristics chips (transistors) as the 5-nm process Intel. Reduced process technology scales up to 5 nm, more or less predictable and will use the same structure of the transistors, and now - a FinFET ribs with three "active" parties.  In the future, changes will be required, or reduce the size of the transistor can not be.  For example, today one FinTET transistor comprises four vertical ridge (rib).  For the release of 5-nm transistors will be necessary to reduce the number of edges to one.  Reducing the number of elements within each of the transistor will increase the density of the transistor. Compensate for the decrease in the number of edges (the total gate area) can be at the expense of increasing the height of each rib.  Today, the height of the ribs is 50 nm (four ribs in the transistor).  For a 7-nm height of the ribs can be increased to 65-70 nm (with a direct link to the two ribs on the transistor).  For the 5-nm height of the ribs need to be increased to 90-100 nm, and leave only one edge.  However, the height of the growth of the ribs leads to other consequences - increasing parasitic capacitance and transistor characteristics deteriorate.  To compensate this disadvantage can be due to the use of a new approach - air gaps around gates instead of using insulating materials, which is also technically difficult.  Finally, insulating ribs can use conventional low-k-materials with low dielectric constants. For production rules 5 nm or less will require significant changes in the structure and materials of the transistors.  Above the picture is a possible structure of such a transistor in which a silicon-germanium material and other exotic compound combinations can be used for the channel and the gate.  Note the vertical edges to beam nanowires.  This, incidentally, eliminates the problem of increasing the parasitic capacitance in the circuit.  Furthermore, the number of nanowires may vary depending upon the desired characteristics of the transistors.  At the same time span wire gates on all sides that the most efficient use of space provided for this purpose.   Related Products :

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