AMD talk about SSE5 specification

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POSTER: computer news   ||   AMD TALK ABOUT SSE5 SPECIFICATION	DATE:2009-05-11
In two years new micro-architecture from Intel and AMD will appear- SandyBridge and Bulldozer respectively. One of the distinguishing features will be the support of new instructions . For Intel this will be AVX instructions , while for AMD SSE5. Between them there will be both similarities and differences. Recently, AMD published the sixth management volume on programming for processors (from its own production). Here we deal with the future instructions . These instructions are intended for special actuating element  FMA (Floating multiply-Accumulate) and produce calculations form D = A * B+C. AMD Specifications provide four registers for such operations, for storing values A, B, C and recording the result D. Analogous concept was originally adhered by Intel in its instructions collection AVX; however, several months ago the specification was changed. The new version FMA from Intel uses three registers instead of four. After producing the calculations of form A * B+C, it writes result not in the fourth register, but in the previous, which were used for storing operands values  . Moreover, record can be produced in any of three registers : A, B or C. However, there is hope, that AMD will change SSE5 specification for compatibility with Intel instructions . Related Products :

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