Belgian scientists will help to reduce the scale of NAND-flash below 20 nm

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POSTER: computer news   ||   BELGIAN SCIENTISTS WILL HELP TO REDUCE THE SCALE OF NAND-FLASH BELOW 20 NM	DATE:2013-06-23
The Belgian research center IMEC at the May conference International Memory Workshop in 2013 proved that Europe still understood something in semiconductors.  Scientists from the Old World have made a report in which talked about the possibility of producing a reliable flash memory with less than 20 nm. The main problem with flash chips that cell to maintain charge becomes so small, and the insulating layer is so thin and small in size, that the performance of the flash memory start to deteriorate.  This leads to a reduction of rewrites, and the loss of data. Scientists proposed to create a three-layer dielectric between the floating gate and the control transistor cell. As the interlayer insulating layer, a combination of aluminum oxide (Al2O3) with low dielectric constant (low-k) and two "wrappers" combination of layers of aluminum and hafnium oxide (HfAlO), which are characterized by high dielectric constant (high-k ). High-k/low-k/high-k-izolyatora layer, according to IMEC representatives  , "shows excellent results in terms of reliability and retention of the charge."   Scientists believe that the three-layer dielectric process technology will reduce the production of NAND-flash chips based on planar transistors below 20 nm without affecting their performance.  However, we have some doubts about the compatibility of a 25-nm insulating layer (10/05/10 nm) with a 14-nm and 10-nm transistor gates.   Related Products :

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