Scientists from Berkeley offer cheaper transition to a process technologies with lower standards

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POSTER: computer news   ||   SCIENTISTS FROM BERKELEY OFFER CHEAPER TRANSITION TO A PROCESS TECHNOLOGIES WITH LOWER STANDARDS	DATE:2017-01-07
Since the beginning of technological processes development  with the standards of less than 30 nm began serious difficulties.  Costs for the development and implementation began to grow stronger, and the transition process has slowed down and is now available to a limited number of semiconductor manufacturers.  For example, each layer for the production of the chip requires two or more photomasks, which in itself is a costly exercise a.  Each photomask,   must be up to 50 pieces on the SoC and processor today costs about $ 1 million. Cheaper transition to technical processes with lower standards and return the law of Moore's offer scientists from Berkeley.  They have developed so-called process of oblique ion bombardment or TII (tilted ion implantation).  The essence of the proposal is clear on the picture.  A beam of ions (in particular development - it is a beam of argon ions) aimed at ordinary photomask first from one angle, then from another.  The ion beam  partially destroys the silicon substrate under the mask and leaves untouched area out of focus.  After the usual etching pattern is much less than on the chip than on the photomask.  Note, all this takes place in a traditional CMOS process technology that promises affordable transition from the traditional "vertical" projection on the corner.  However, manufacturers have not yet lined up for a license to TII. The presented technology is tested for the production of prototype 9-nm silicon.  The resulting projection step is 18-20 nm.  For comparison, 7-nm process technology TSMC gives minimum metallization step for the "zero layer" the M0 - the place of first contact with the crystal - as many as 40 nm.  In addition, as already mentioned above,  TII technology can be up to 50% to reduce the cost of expenses for the development of process technology from 16 nm technological standards, and a 35% increase in chip release performance in a given process technology, which is based on a double projection in normal conditions (uses two mask per layer). Related Products :

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