The structure of CPU architecture AMD Zen

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POSTER: computer news   ||   THE STRUCTURE OF CPU ARCHITECTURE AMD ZEN	DATE:2015-04-29
The site Planet3DNow.de got a second slide, revealing the structure of block-based processor at the upcoming x86-compatible architecture AMD Zen.    In any case, the unit for calculating the floating point now each core its own, not shared.  Also, a 50% increase in the number of pipelines in the unit to work with integer operations. New slide reveals the structure of a quad unit, which includes a shared cache in the third level, the total volume of 8 MB to four cores.  The volume of L2 cache for each core is at 512K.  It is important to note that AMD is returning to the inclusive logic of the cache memory.  Since the mid 90's (with the appearance of processors K6) AMD developers have moved to the use of logic inclusive to exclusive.  This means, for example, that the data were stored in their own memory and do not duplicate themselves from L1 to L2.  Inclusive cache suggests that the data from the L1 are duplicated in memory L2.  This is somewhat non-optimal, but, apparently, in most cases, faster and easier.   We also learned that the block will include a quad high-speed bus for increasing the number of cores in the composition of the individual models. It seems that AMD processors Zen generation  will get the number of cores, four times four, eight, twelve, etc.  In the desktop segment, we need to understand  the dominance of the four  and eight-core models.  Incidentally, in the flowchart have integrated memory controller.  It can mean a simplified material flow and an opportunity to present processors with customizable interface. Set periphery may depend on the processor application .   Related Products :

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