Multilayer flash memory NAND-type has 32-48 workers. All layers permeates through connection type TSVs. In fact - it is filled with metal channels conductors. But in case of 3D NAND memory cell channels are formed directly around the metallization. Simply put, TSVs - it is an integral part of the memory cells. Meanwhile, the type of connection used TSVs began long before the multi-layered memory.
First practice for the assembly of multi-chip packaging method through channels metallization was by Samsung company . In 2007, the manufacturer introduced a multi-chip stack layout of the four 64-Mbyte crystals DDR2, collected by TSVs. Until this moment the stacks of crystals 20 pieces assembled by using the outer wire harnesses. This required considerable free space around the working of the crystal, as well as significantly increased operating currents as increasing the length of the connecting conductors.
Toshiba Company, as reported to us a press release , is not going to part with the multi-chip stack package using TSVs, even in light of the transition to a multi-layer 3D NAND. The Japanese manufacturer introduced the 8- and 16-crystal assembly gathered using TSVs-connections. In this case, channels TSVs - conductors is simply not participating in the organization of memory cells. However, this approach, as stated above, enables to minimize the area of each crystal in the grid and reduce the current load. According to Toshiba, the performance of the read / write memory consumption is reduced by 50%.
Demonstration development held on August 11 at the event, Flash Memory Summit 2015. The company has prepared two samples: 8-level 128-GB chip and 16-level 256 GB. The rate of exchange at the interface assembly may exceed 1 Gb / s. Stated interface - Toggle DDR.
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