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Manufacturers have taken the course to standardize multi-chip packages

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 Manufacturers have taken the course to standardize multi-chip packages

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A number of reports at the conference Hot Chips 2017 showed the extreme interest of semiconductor manufacturers and developers in multi-chip packages.  More precisely, we are not talking about traditional multi-chip packaging of identical crystals, as, for example, in the case of AMD EPYC processors, but about packaging of heterogeneous crystals connected by a high-speed interface.  The latter allow to significantly increase the density and complexity of solutions, which can not be achieved if the discrete components are combined on the board.

The developers' hopes are related to the expected standardization of the so-called chiplets.  Thin crystals for modular assemblies on a common substrate should receive the status of IP solutions - licensed for the development of unified blocks, the assembly, production and assembly of which will be maximally automated.  This is currently being handled by a group of companies within the framework of the Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) project of the Defense Advanced Research Projects Agency.  The resulting standard should be open and it will be opposed to today's proprietary technologies TSMC CoWoS, Intel EMIB and others.  The result should be announced no later than eight months.  We will see.

While there is no general standard, Intel and TSMC are actively promoting their approaches.  TSMC uses CoWoS 2.5D (Chip-on-Wafer-on-Substrate) for assembling AMD and NVIDIA GPUs with HBM memory and for packaging Apple's SoC with memory chips.  With the same packaging, Xilinx FPGAs with integrated memory are available.  For a mass user, this is still an expensive experience and, in addition, Intel and AMD processors are not yet available in this form.  Also, from the packaging of CoWoS, Microsoft refused when designing a new processor for the Xbox One X. Expensive.

The Intel EMIB technology, proposed in 2014 (Embedded Multi-die Interconnect Bridge), promised to become cheaper multi-chip packaging.  It does not use end-to-end TSVs, as in the case of the TSMC proposal, and relies on a simple bridge from the substrate.  With the help of EMIB, Intel produces FPGA Stratix (Altera) with integrated transceivers and memory.  For this purpose, Intel offered two interfaces: for memory HBM digital UIB, for RF and other blocks - analog AIB.  EMIB packaging is available in three Intel plants for six different process processes.  Within the assembly, up to 20,000 links with a bandwidth of up to 2 Gb / s are offered.  According to the leading architect of Intel's FPGA group, Sergey Shkaraev (a graduate of KhAI), the EMIB package allows creating a complex chip six times larger than the 2.5D package.

At the same time, both Intel and TSMC note a number of limitations inherent in multi-chip packages.  So, the CoWoS process does not allow heating chips when mounted on a substrate over 95 degrees Celsius.  This limitation is caused by the use of a stack in the form of HBM memory, each lower layer of which is hotter by 2 degrees.  At the same time, Intel, for example, makes extremely stringent requirements for suppliers of crystals for EMIB packaging.  One faulty crystal will negate all the savings that are expected from multi-chip packages.

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 Manufacturers have taken the course to standardize multi-chip packages

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